Goa circuit and display panel

A gate driver on array (GOA) circuit, comprising a plurality of cascaded GOA circuit units, wherein an n-stage GOA circuit unit comprises a pull-up control circuit unit 101, a pull-up circuit unit 102, a transfer circuit unit 103, a pull-down circuit unit 104, and a capacitor Cb;

• wherein the pull-up control circuit unit 101, the pull-up circuit unit 102, the transfer circuit unit 103, the pull-down circuit unit 104, a pull-down maintenance circuit unit 105, and the capacitor Cb are all electrically connected to a first node Q(n);
• the pull-up circuit unit 101 receives a clock signal CKN−1 of an (n−1)-stage GOA circuit unit, and a start trigger signal STV or a cascaded signal STN−1 of the (n−1)-stage GOA circuit unit to charge the first node Q(n) to a high electric potential;
• the pull-up circuit unit 102 receives a clock signal CKN to pull up an output signal GN of the n-stage GOA circuit unit to a high electric potential of the clock signal CKN;
• the transfer circuit unit 103 receives the clock signal CKN and outputs a cascaded signal STN of the n-stage GOA circuit unit to control a pull-up control circuit unit of an (n+1)-stage GOA unit to turn on or turn off;
• the pull-down circuit unit 104 receives a clock signal CKN+2 of an (n+2)-stage GOA circuit unit, a first low-electric-potential direct current signal VSSQ, and a second low-electric-potential direct current signal VSSG to pull down a precharge electric potential of the first node Q(n), an electric potential of the cascaded signal STN of the n-stage GOA circuit unit, and an electric potential of the n-stage scan driving signal G(n) to a low electric potential;
• and
• the capacitor Cb is configured to provide and maintain the precharge electric potential of the first node Q(n), and the capacitor Cb is connected to the output signal GN of the n-stage GOA circuit unit.