US 2022/0189370 A1 · DATA DRIVER CIRCUIT

Abstract

The present disclosure relates to a data driver circuit capable of overcoming a limitation in frequency by correcting a skew between a clock and data even when a frequency and the number of channels are increased, and the data driver circuit according to an aspect may include a shift register configured output sampling signals in response to a clock, a first latch part configured to sample and latch data of each channel in response to each of the sampling signals, and a bi-directional deskew buffer part disposed between a stage of a first channel and a stage of a second channel belonging to the shift register and between a first latch of a first channel and a second latch of a second channel belonging to the first latch part and configured to buffer a clock input from the stage of the first channel.

Claims20

Dependent claims

A data driver circuit comprising:

a shift register configured output sampling signals in response to a clock;
a first latch part configured to sample and latch data of each channel in response to each of the sampling signals;
and
a bi-directional deskew buffer part disposed between a stage of a first channel and a stage of a second channel belonging to the shift register and between a first latch of a first channel and a first latch of a second channel belonging to the first latch part, and configured to buffer a clock input from the stage of the first channel to output the buffered clock to the stage of the second channel, and buffer and latch data of the second channel input after data of the first channel, which is latched by the first latch of the first channel, in synchronization with the buffered clock to output the latched data to the first latch of the second channel.

1 more element

A data driver circuit comprising a bi-directional deskew buffer part disposed between a stage of a first channel and a stage of a second channel belonging to a shift register and between a first latch of a first channel and a first latch of a second channel belonging to a first latch part,

wherein the bi-directional deskew buffer part includes:
a clock buffer configured to buffer a clock input from the stage of the first channel and output the buffered clock to the stage of the second channel;
and
a data buffer part configured to buffer and latch data of the second channel input after data of the first channel, which is latched by the first latch of the first channel, in synchronization with a clock output from the clock buffer, and output the latched data to the first latch of the second channel.

1 more element

Dependencies are inferred from the claim text.

Data driver circuit

Life of this patent

Data driver circuit

Life of this patent

Abstract

Claims20