Intergrated circuit, method for operating the same, and display system including the same
AssigneeLx Semicon Co., Ltd.
InventorsBo Sung KIM, Byung Woo SONG
Life of this patent
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AssigneeLx Semicon Co., Ltd.
InventorsBo Sung KIM, Byung Woo SONG
Estimating the term…
Provided is an integrated circuit capable of gating a clock signal to reduce power consumption during a vertical front porch interval, the integrated circuit including: a control signal generator configured to change a gating control signal from a low level to a high level according to a timing when a data enable signal changes from the high level to the low level, and change the gating control signal from the high level to the low level after a predetermined horizontal back porch interval from a rising edge of a horizontal synchronization signal; and a clock gating circuit configured to stop toggling of a first clock signal input through a first input terminal to output a second clock signal maintained at the low level through a first output terminal when the gating control signal of the high level is input to a control terminal.
An integrated circuit for gating a clock signal, comprising:
A display system comprising:
An operation method of an integrated circuit for gating a clock signal, comprising:
Dependencies are inferred from the claim text.