Methods, systems and apparatus to reduce memory latency when fetching pixel kernels

A non-transitory computer readable storage medium comprising instructions that, when executed, cause processor circuitry to at least:

• receive at first interface circuitry a first request from a hardware accelerator at a first time, the first request including first coordinates of a first pixel disposed in a first image block;
• receive at second interface circuitry a second request from the hardware accelerator at a second time after the first time, the second request including second coordinates;
• in response to the second request, determine whether the first image block has been stored in cache storage based on a mapping of the second coordinates to a block tag;
• and
• in response to determining that the first image block has been stored in the cache storage, access, in parallel, two or more memory devices associated with the cache storage to transfer a plurality of image blocks including the first image block to the hardware accelerator.

A method to reduce pixel transfer latency, the method comprising:

• receiving at first interface circuitry a first request from a hardware accelerator at a first time, the first request including first coordinates of a first pixel disposed in a first image block;
• receiving at second interface circuitry a second request from the hardware accelerator at a second time after the first time, the second request including second coordinates,
• in response to the second request, determining whether the first image block has been stored in cache storage based on a mapping of the second coordinates to a block tag;
• and
• in response to determining that the first image block has been stored in the cache storage, accessing, in parallel, two or more memory devices associated with the cache storage to transfer a plurality of image blocks including the first image block to the hardware accelerator.