Fractal calculating device and method, integrated circuit and board card
AssigneeCambricon Technologies Corporation Limited
InventorsShaoli LIU, Guang JIANG, Yongwei ZHAO, Jun LIANG
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Abstract
A fractal computing device according to an embodiment of the present application may be included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also include a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.
Claims20
A calculation unit for calculating data according to input instructions, wherein the calculation unit is divided into an M-stage pipeline, and the calculation unit includes:
- a serial decomposer configured to decompose the input instructions into N serial instructions, and generate intermediate data reflecting the dependency among the N serial instructions;
- a local memory including a static memory segment to store the intermediate data, and a loop memory segment to store sub-data required to execute the N serial instructions and data of each stage generated by a calculation of the sub-data in the M-stage pipeline, where the sub-data is a part of the data.
A fractal calculating device, comprising a plurality of layers of calculating node, wherein each calculating node includes a memory component, a processor, and a next layer of calculating node;
- where the memory component including a static memory segment and a loop memory segment;
- the processor is configured to decompose input instructions of any calculating node to obtain a plurality of sub-instructions;
- if there are shared operands among the plurality of sub-instructions, the processor allocates memory space for the shared operands in the static memory segment, and allocates memory space for other operands of the plurality of sub-instructions in the loop memory segment;
- where the shared operands are operands that must be used when a next layer of calculating node of any calculating node executes the plurality of sub-instructions;
- and the other operands are operands other than the shared operands among the operands of the plurality of sub-instructions.
Dependencies are inferred from the claim text.