Neural networks processing units performance optimization

A system comprising:

• a deep neural network (DNN) parallel processor that is flexible, hardware programmable, scalable, and reconfigurable, the DNN parallel processor comprising a plurality of neural networks processing units (NPUs) configured to process artificial intelligence (AI)/machine learning (ML) input data, each of the plurality of NPUs comprising:
• an activation (A) map memory;
• a weight (W) map memory;
• a compressed A memory;
• a pruned W memory;
• a control logic block coupled to outputs of the A map memory and the W map memory and to inputs of the compressed A memory and the pruned W memory;
• a routing multiplexer coupled to outputs of the control logic block, the compressed A memory, and the pruned W memory;
• a multiplier-accumulator (MAC) coupled to an output of the routing multiplexer;
• and
• a rectified linear unit (ReLU) or other non-linear function coupled to an output of the MAC;
• wherein the plurality of NPUs are connected together to perform DNN functions;
• and
• a system processor coupled to each of the plurality of NPUs of the DNN parallel processor, wherein the system processor is configured to enable easy hardware programming with DNN system parameters, DNN weights, sensor inputs, W_LUT values, and re-configurability to support different DNN models.

A deep neural network (DNN) parallel processor or generic vector multiplier that is flexible, hardware programmable, scalable, and reconfigurable, the DNN parallel processor comprising a neural networks processing unit (NPU) configured to process artificial intelligence (AI)/machine learning (ML) input data, the NPU comprising:

• a weight lookup table (W_LUT) memory;
• a plurality of multiplier accelerators (MAs), each of the MAs comprising:
• an accumulator coupled to an output of an activation (A) memory;
• and
• an activation lookup table (A_LUT) memory coupled to an output of the accumulator and an output of a weight (W) memory;
• a routing multiplexer coupled to outputs of the MAs and the W_LUT memory;
• a multiplier-accumulator (MAC) coupled to an output of the routing multiplexer;
• and
• a rectified linear unit (ReLU) or other non-linear functions coupled to an output of the MAC;
• wherein each of the plurality of MAs is configured to reduce an amount of multiplications of an activation function.