Method for memory allocation during execution of a neural network
AssigneesSTMicroelectronics S.r.I., STMicroelectronics (Rousset) SAS
InventorsLaurent Folliot, Mirko Falchetto, Pierre Demaj
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Abstract
According to an aspect, a method is proposed for defining placements, in a volatile memory, of temporary scratch buffers used during an execution of an artificial neural network, the method comprising: determining an execution order of layers of the neural network, defining placements, in a heap memory zone of the volatile memory, of intermediate result buffers generated by each layer, according to the execution order of the layers, determining at least one free area of the heap memory zone over the execution of the layers, defining placements of temporary scratch buffers in the at least one free area of the heap memory zone according to the execution order of the layers.
Claims20
A method, comprising:
- determining an execution order of layers of an artificial neural network;
- defining, in a heap memory zone of a volatile memory, a placement of an intermediate result buffer generated by each layer in accordance with the execution order of the layers;
- determining a free area of the heap memory zone for an execution of each layer;
- and
- defining, in the free area of the heap memory zone, a placement of a temporary scratch buffer based on the execution order of the layers.
A non-transitory computer-readable media storing computer instruction, that when executed by one or more processors, cause the processor to perform:
- determining an execution order of layers of an artificial neural network;
- defining, in a heap memory zone of a volatile memory, a placement of an intermediate result buffer generated by each layer in accordance with the execution order of the layers;
- determining a free area of the heap memory zone for an execution of each layer;
- and
- defining, in the free area of the heap memory zone, a placement of a temporary scratch buffer based on the execution order of the layers.
An integrated circuit, comprising:
- a non-volatile memory storage comprising an artificial neural network instruction;
- a volatile memory storage;
- and
- a processor coupled to the non-volatile memory storage and the volatile memory storage, wherein the processor is configured to execute the artificial neural network instructions to:
- determine an execution order of layers of an artificial neural network,
- define, in a heap memory zone of the volatile memory storage, a placement of an intermediate result buffer generated by each layer in accordance with the execution order of the layers,
- determine a free area of the heap memory zone for an execution of each layer, and define, in the free area of the heap memory zone, a placement of a temporary scratch buffer based on the execution order of the layers.
Dependencies are inferred from the claim text.