Memory Configuration to Support Deep Learning Accelerator in an Integrated Circuit Device
AssigneeMicron Technology, Inc.
InventorDavid Andrew Roberts
Life of this patent
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Abstract
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit (IC) device includes a first stack of IC dies connected to a plurality of second stacks of IC dies. The first stack has a first die of a memory controller and processing units of the Deep Learning Accelerator and at least one second die that is stacked on the first die to provide a first type of memory. Each of the second stacks has a base die and at least a third die and a fourth die having different types of memory. The base die has logic circuit configured to copy data within the same stack in response to commands from the memory controller and has a second type of memory usable as die cross buffer.
Claims20
A device, comprising:
- a first stack of integrated circuit dies, including:
- a first integrated circuit die containing a memory controller and processing units configured to perform at least computations on matrix operands;
- and
- at least one second integrated circuit die stacked on the first integrated circuit die and containing memory cells of a first type;
- a plurality of second stacks of integrated circuit dies, each respective stack in the plurality of second stacks including:
- a base integrated circuit die containing logic circuit and memory cells of a second type;
- and
- at least one third integrated circuit die stacked on the base integrated circuit die and containing memory cells that are different from the first type and different from the second type;
- and
- a plurality of communication connections, each of the communication connections configured between the memory controller in the first stack and the logic circuit of the respective stack.
A method, comprising:
- communicating, via a communication connection, between a first stack of integrated circuit dies of a device and a second stack of integrated circuit dies of the device;
- writing, through the communication connection and by a memory controller configured in a first integrated circuit die in the first stack, a block of data stored in memory cells of a first type configured in at least one second integrated circuit die stacked on the first integrated circuit die in the first stack into memory cells of a second type configured in a base integrated circuit die in the second stack;
- and
- copying, by logic circuit configured in the base integrated circuit die, the block of data from the base integrated circuit die into memory cells of different types configured in at least one third integrated circuit die stacked on the base integrated circuit die in the second stack.
An apparatus, comprising:
- a silicon interposer;
- a first stack of integrated circuit dies configured on the silicon interposer, the first stack including:
- a first integrated circuit die containing a Field-Programmable Gate Array (FPGA) or Application Specific Integrated circuit (ASIC), including:
- a memory controller;
- a control unit;
- and
- at least one processing unit configured to operate on two matrix operands of an instruction executed in the FPGA or ASIC;
- and
- at least two second integrated circuit die stacked on the first integrated circuit die and containing memory cells of a first type;
- a plurality of second stacks of integrated circuit dies configured on the silicon interposer, each respective stack in the plurality of second stacks including:
- a base integrated circuit die containing logic circuit and memory cells of a second type;
- a third integrated circuit die stacked on the base integrated circuit die and containing memory cells of a third type;
- and
- a fourth integrated circuit die stacked on the third integrated circuit die and containing memory cells of a fourth type;
- and
- a plurality of communication connections configured on the silicon interposer, each respective connection in the plurality of the communication connections configured to connect the memory controller in the first stack and the logic circuit of the respective stack.
Dependencies are inferred from the claim text.