US 2022/0188491 A1 · DESIGN TO FABRICATED LAYOUT CORRELATION

Abstract

In an integrated circuit (IC) assessment method, an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) is trained to transform layout rendering tiles of a rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC. Using the trained AI component, standard cell layout renderings of a library of GDSII or OASIS standard cell layout renderings are transformed into as-fabricated standard cell layout renderings forming a library of as fabricated standard cell layout renderings. Instantiated standard cells and their placements in the layout image of an IC-under-test are identified by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as fabricated standard cell layout renderings.

Claims20

Dependent claims

An integrated circuit (IC) assessment device for assessing an IC-under-test, the IC assessment device comprising:

an electronic processor;
and
a non-transitory storage medium storing:
a library of as-fabricated standard cell layout renderings constructed using at least one reference layout image acquired of a reference IC;
and
instructions readable and executable by the electronic processor to perform an IC assessment method including identifying instantiated standard cells and their placements in the layout image of the IC-under-test by matching the instantiated standard cells with corresponding as-fabricated standard cell layout renderings retrieved from the library of as-fabricated standard cell layout renderings.

3 more elements

A non-transitory storage medium storing instructions readable and executable by an electronic processor to perform a method of constructing a library of as-fabricated standard cell layout renderings, the method including:

training an artificial intelligence (AI) component comprising at least one artificial neural network (ANN) to transform layout rendering tiles of a layout rendering of a reference IC into corresponding reference layout image tiles extracted from at least one layout image of the reference IC;
and
using the trained AI component, transforming standard cell layout renderings of a library of standard cell layout renderings into the as-fabricated standard cell layout renderings forming the library of as-fabricated standard cell layout renderings.

Dependencies are inferred from the claim text.

Design to fabricated layout correlation

Life of this patent

Design to fabricated layout correlation

Life of this patent

Abstract

Claims20