Systems and methods for dynamic control of a secure mode of operation in a processor

A method of changing a mode of operation of a processor without rebooting the processor, the method comprising:

• in response to a trigger to change from a secure mode to a performance mode of operation for a control aspect in a privilege level, checking whether a bit in a Privilege Entry (PRVS) register field for the control aspect in the privilege level is set to the performance mode;
• in response to the bit in the PRVS register field for the control aspect in the privilege level not being set to the performance mode, setting the bit in the service register field for the control aspect in the privilege level to the performance mode;
• checking whether the control aspect in the privilege level of an Enforce Below (ENFB) register field is set to performance mode for all higher privilege levels;
• and
• in response to the control aspect in the privilege level of the ENFB register being set to the performance mode for all higher privilege levels, changing the processor to the performance mode for the control aspect in the privilege level.

A computer system for processing information, the computer system comprising:

• at least one processor having one or more register files, wherein at least one of the registers is a configuration register,
• the configuration register having a privilege entry (PRVS) register field for each of one or more privilege levels, each PRVS register field for each privilege level having one or more control aspect entries to hold a bit;
• and an enforce below (ENFB) register field for one less than each of one or more privilege levels, each ENFB register field for each privilege level having one or more control aspect entries to hold a bit, the PRVS register field control aspects being equal in number to and corresponding to the ENRB register field control aspects,
• wherein, the processor is configured and adapted to:
• initiate a change in configuration in a processor from a performance mode to a secure mode for a control aspect in a privilege level;
• determine whether the bit for the control aspect in the privilege level is set in the PRVS register field to secure mode;
• and
• if the bit for the control aspect in the privilege level in the PRVS register field is not set to secure mode, then set the bit for the control aspect in the privilege level in the PRVS register field to secure mode, thereby enabling the secure mode in the processor for the control aspect in the privilege level.