Hardware trojan detection using reinforcement learning

A system for test pattern generation to detect a hardware Trojan using delay-based analysis, the system comprising:

• a processor;
• and
• a tangible, non-transitory memory configured to communicate with the processor, the tangible, non-transitory memory having instructions stored thereon that, in response to execution by the processor, cause the processor to perform operations comprising:
• determining a set of initial test patterns to activate the hardware Trojan within an integrated circuit design;
• evaluating nodes of the integrated circuit design and assigning a rareness attribute value and a testability attribute value associated with respective nodes of the integrated circuit design;
• and
• generating a set of additional test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model, wherein the set of initial test patterns is applied as an input to the reinforcement learning model along with rareness attribute values and testability attribute values associated with the nodes of the integrated circuit, wherein the reinforcement learning model is trained with a stochastic learning scheme to increase a probability of triggering one or more hardware Trojans in the integrated circuit design and identify optimal test patterns for triggering nodes of the integrated circuit design based on a combination of the rareness attribute values and the testability attributes values associated with the triggered nodes of the integrated circuit design.

A non-transitory, tangible computer readable medium having instructions stored thereon that, in response to execution by a processor in a computing device, cause the computing device to be capable of performing operations comprising:

• determining a set of initial test patterns to activate a hardware Trojan within an integrated circuit design using a dynamic simulation of the integrated circuit design;
• evaluating nodes of the integrated circuit design and assigning a rareness attribute value and a testability attribute value associated with respective nodes of the integrated circuit design;
• and
• generating a set of additional test patterns to activate the hardware Trojan within the integrated circuit design using a reinforcement learning model, wherein the set of initial test patterns is applied as an input to the reinforcement learning model along with rareness attribute values and testability attribute values associated with the nodes of the integrated circuit, wherein the reinforcement learning model is trained with a stochastic learning scheme to increase a probability of triggering one or more hardware Trojans in the integrated circuit design and identify optimal test patterns for triggering nodes of the integrated circuit design based on a combination of the rareness attribute values and the testability attributes values associated with the triggered nodes of the integrated circuit design.