Hardware mitigation for spectre and meltdown-like attacks

A method for blocking a side-channel attack against a processor, said processor comprising at least one register which receives loads during said side-channel attack, said method comprising:

• increasing a first global generation counter upon each decoding and predicting of a branch type instruction;
• increasing a second global generation counter upon every completion of a branch type instruction, wherein said first global generation counter is reset, upon a triggered rollback, to a value of said second global generation counter;
• storing a generation tag value in a generation tag memory associated with said at least one register of said processor which is set to a value of said first global generation counter upon a first load into said associated register;
• determining, for a second load of a register of said at least one register loaded from an address depending on said value of said register of said first load, a generation tag value associated with said register of said second load, said generation tag value being a function of said value of said first global generation counter, said value of said second global generation counter, and said generation tag value associated with said register of said first load;
• and
• blocking, by a wait queue, said second load, if said determined generation tag value is more than one generation ahead of said value of said second global generation counter.

A computer program product for blocking a side-channel attack against a processor that includes at least one register which receives loads during said side-channel attack, the computer program product comprising one or more computer-readable storage mediums having program instructions embodied therewith, the program instructions executable by one or more processors including the processor to cause the one or more processors to perform operations comprising:

• increasing a first global generation counter upon each decoding and predicting of a branch type instruction;
• increasing a second global generation counter upon every completion of a branch type instruction, wherein said first global generation counter is reset, upon a triggered rollback, to a value of said second global generation counter;
• storing a generation tag value in a generation tag memory associated with said at least one register of said processor which is set to a value of said first global generation counter upon a first load into said associated register;
• determining, for a second load of a register of said at least one register loaded from an address depending on said value of said register of said first load, a generation tag value associated with said register of said second load, said generation tag value being a function of said value of said first global generation counter, said value of said second global generation counter, and said generation tag value associated with said register of said first load;
• and
• blocking, by a wait queue, said second load, if said determined generation tag value is more than one generation ahead of said value of said second global generation counter.