Timed unlocking and locking of hardware intellectual properties

A method of protecting an integrated circuit design by locking sequential and combinational logic of the integrated circuit design, the method comprising:

• obtaining a gate-level netlist for the integrated circuit design, wherein functionality of the integrated circuit design is enabled by entering of key inputs;
• identifying control path state elements that constitute a finite state machine (FSM) within the integrated circuit design and any pseudo-state elements within the gate-level netlist for the integrated circuit design, wherein the pseudo-state elements constitute data path flip-flop circuit elements that impact a state transition of the FSM;
• adding one or more extra FSM elements using a multiplexer to an input of individual ones of a plurality of target elements of the integrated circuit design in parallel with original design logic at the input of the target element, wherein the plurality of target elements constitute the identified control path state elements and pseudo-state elements, wherein the one or more extra FSM elements are driven by an output of an obfuscation finite state machine that accepts a subset of the key inputs corresponding to a functional key sequence for facilitating a permanent mode of operation for the integrated circuit design or the subset of the key inputs corresponding to a test key sequence for facilitating a temporary mode of operation of the integrated circuit design until occurrence of a defined event, wherein occurrence of the defined event causes a corruption of the functionality of the integrated circuit design, wherein an input of incorrect keys that do not correspond to the functional key sequence and the test key sequence cause the corruption of the functionality of the integrated circuit design;
• adding a data path enable finite state machine to implement the corruption of the functionality of the integrated circuit design, wherein input values to the data path enable finite state machine correspond to a subset of the key inputs that do not match the functional key sequence or the test key sequence;
• and
• generating an obfuscated gate-level netlist of the integrated circuit design after completion of the adding operations.

A system of protecting an integrated circuit design by locking sequential and combinational logic of the integrated circuit design, the system comprising:

• a processor;
• and
• a tangible, non-transitory memory configured to communicate with the processor, the tangible, non-transitory memory having instructions stored thereon that, in response to execution by the processor, cause the processor to be capable of performing operations comprising:
• obtaining a gate-level netlist for the integrated circuit design, wherein functionality of the integrated circuit design is enabled by entering of key inputs;
• identifying control path state elements that constitute a finite state machine (FSM) within the integrated circuit design and any pseudo-state elements within the gate-level netlist for the integrated circuit design, wherein the pseudo-state elements constitute data path flip-flop circuit elements that impact a state transition of the FSM;
• adding one or more extra FSM elements using a multiplexer to an input of individual ones of a plurality of target elements of the integrated circuit design in parallel with original design logic at the input of the target element, wherein the plurality of target elements constitute the identified control path state elements and pseudo-state elements, wherein the one or more extra FSM elements are driven by an output of an obfuscation finite state machine that accepts a subset of the key inputs corresponding to a functional key sequence for facilitating a permanent mode of operation for the integrated circuit design or the subset of the key inputs corresponding to a test key sequence for facilitating a temporary mode of operation of the integrated circuit design until occurrence of a defined event, wherein occurrence of the defined event causes a corruption of the functionality of the integrated circuit design, wherein an input of incorrect keys that do not correspond to the functional key sequence and the test key sequence cause the corruption of the functionality of the integrated circuit design;
• adding a data path enable finite state machine to implement the corruption of the functionality of the integrated circuit design, wherein input values to the data path enable finite state machine correspond to a subset of the key inputs that do not match the functional key sequence or the test key sequence;
• and
• generating an obfuscated gate-level netlist of the integrated circuit design after completion of the adding operations.