Enumeration of peripheral devices on a serial communication bus

A device including a communication interface comprising:

• a data input terminal;
• a first data output terminal;
• a second data output terminal;
• a shift register coupled to the data input terminal;
• and
• switch logic responsive to a daisy-chain mode of operation to couple an output of the shift register to the first data output terminal and the switch logic being responsive to a first parallel mode of operation to couple the data input terminal to the first data output terminal bypassing the shift register and to couple the output of the shift register to the second data output terminal, and the switch logic is responsive to a second parallel mode of operation to couple the output of the shift register to the second data output terminal.

A communication system comprising:

• N devices coupled to a controller, N being an integer greater than 1;
• the N devices being serially coupled in a chain in a daisy-chain mode of operation, and while in the daisy-chain mode of operation a first of the N devices is coupled to receive data from the controller and a remainder of the N devices are coupled to receive data from a previous device in the chain, and a last of the N devices is coupled to supply data to the controller;
• the N devices being responsive to respective enumerate commands received in the daisy-chain mode of operation to become uniquely identified by a respective one of N addresses sent with the enumerate commands, a respective one of the N addresses being associated with a respective one of the enumerate commands;
• N-1 devices of the N devices being configured to switch from operating in the daisy-chain mode of operation to operating in a first parallel mode of operation responsive to a first mode command, the N-1 devices being individually addressable in the first parallel mode of operation according to their respective addresses;
• and
• a last one of the N devices being configured to switch from operating in the daisy-chain mode of operation to operating in a second parallel mode of operation in which the last one of the N devices is individually addressable according to one of the N addresses that was assigned to the last one of the N devices.