Multiple memory type shared memory bus systems and methods

A method comprising:

• receiving, by a memory controller of a memory system, first data provided using a first clock frequency from a first memory device of the memory system;
• receiving, by the memory controller, second data provided using a second clock frequency from a second memory device of the memory system;
• and
• providing, by the memory controller, the first data and the second data to a processing system via a system bus using a performance mode clock frequency higher than the first clock frequency and the second clock frequency, when a target memory access latency of the memory system is below a latency threshold, a target power consumption of the memory system is equal to or above a power consumption threshold, or both.

A method comprising:

• receiving, by a memory controller of a memory system, first data and second data provided using a performance mode clock frequency from a processing system via a system bus, when a target memory access latency of the memory system is below a latency threshold, a target power consumption of the memory system is equal to or above a power consumption threshold, or both, wherein the performance mode clock frequency is higher than a first clock frequency of a first memory device and a second clock frequency of a second memory device of the memory system;
• providing, by the memory controller, the first data to the first memory device using the first clock frequency;
• and
• providing, by the memory controller, the second data to the second memory device using the second clock frequency.

A memory system, comprising:

• a first memory device configured to operate according to a first clock frequency;
• a second memory device configured to operate according to a second clock frequency;
• and
• a memory controller configured to communicate with a processing system via a system bus using a performance mode clock frequency higher than the first clock frequency and the second clock frequency when a target memory access latency of the memory system is below a latency threshold, a target power consumption of the memory system is equal to or above a power consumption threshold, or both.