Page table structure

A method comprising:

• performing a page table walk to obtain, for use in translating memory addresses, page table entries from a page table structure comprising a plurality of levels of page tables stored in a memory system, each page table entry identifying an address pointer for identifying one of:
• a translated address, and an address of a child page table at a next level of the page table structure;
• in which:
• when a given page table entry is a relative type of page table entry specifying a relative offset value indicating an offset of the address pointer relative to a reference-point base address determined for the given page table entry, the address pointer is determined from the reference-point base address and the relative offset value.

A computer program comprising:

• page table walk program logic to obtain page table entries from a page table structure comprising a plurality of levels of page tables, each page table entry identifying an address pointer for identifying one of:
• a translated address, and an address of a child page table at a next level of the page table structure;
• in which:
• when a given page table entry is a relative type of page table entry specifying a relative offset value indicating an offset of the address pointer relative to a reference-point base address determined for the given page table entry, the page table walk program logic is configured to determine the address pointer from the reference-point base address and the relative offset value.

An apparatus comprising:

• memory management circuitry to translate memory addresses based on page table entries defined in a page table structure comprising a plurality of levels of page tables stored in a memory system;
• and
• page table walk circuitry to obtain the page table entries from the page table structure for use by the memory management circuitry, each page table entry identifying an address pointer for identifying one of:
• a translated address, and an address of a child page table at a next level of the page table structure;
• in which:
• when a given page table entry specifies a descendant-entries-restricted indicator, the page table walk circuitry is configured to signal a fault when a descendant page table entry of the given page table entry identifies an address pointer lying outside a bounding address region identified by the given page table entry.

A computer program comprising:

• page table walk program logic to obtain page table entries from a page table structure comprising a plurality of levels of page tables, each page table entry identifying an address pointer for identifying one of:
• a translated address, and an address of a child page table at a next level of the page table structure;
• in which:
• when a given page table entry specifies a descendant-entries-restricted indicator, the page table walk program logic is configured to signal a fault when a descendant page table entry of the given page table entry identifies an address pointer lying outside a bounding address region identified by the given page table entry.