US 2022/0188244 A1Published application

Dynamic logical page sizes for memory devices

AssigneeMicron Technology, Inc.

InventorsSharath Chandra Ambula, David Aaron Palmer, Venkata Kiran Kumar Matturi, Sri Ramya Pinisetty, Sushil Kumar

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Abstract

Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Claims25

Dependent claims

An apparatus comprising:

a memory device;
and
a controller for the memory device and configured to cause the apparatus to:
receive a write command for writing a first amount of data to the memory device, the write command associated with a logical address;
read, based at least in part on the logical address, a first entry of a first logical-to-physical (L2P) table, wherein the first L2P table is for mapping a plurality of logical addresses to physical addresses of a corresponding first plurality of logical pages that each have a first logical page size, and wherein the first entry of the first L2P table comprises a first physical address of a first logical page of the first plurality of logical pages;
identify, based at least in part on a size of the first amount of data, a second logical page size;
write, based at least in part on the first physical address, at least a portion of the first amount of data to a second logical page of the memory device having the second logical page size, the first logical page comprising the second logical page;
and
store, based at least in part on identifying the second logical page size, a first entry of a second L2P table for mapping a second plurality of logical addresses to physical addresses of a corresponding second plurality of logical pages of the memory device, each logical page of the second plurality of logical pages having the second logical page size, wherein the first entry in the second L2P table comprises a second physical address of the second logical page.

6 more elements

An apparatus comprising:

a memory device;
and
a controller for the memory device and configured to cause the apparatus to:
receive a read command associated with a first logical address that is associated with a starting location of data stored in the memory device;
read a first entry of a first logical-to-physical (L2P) table based at least in part on the logical address, wherein the first entry comprises a first physical address of a first logical page of the memory device having a first logical page size, and wherein a value of a first portion of the first physical address indicates a second logical page size of a second logical page of memory that contains the data, the first logical page comprising the second logical page;
determine, based at least in part on the value of the first portion of the first physical address, whether the second logical page size is different than the first logical page size;
determine, based at least in part on the determination of whether the second logical page size is different than the first logical page size, a second physical address that points to the starting location of the data within the second logical page;
read the data from the starting location of the data within the second logical page based at least in part on the second physical address;
and
transmit the data to a host device for the memory device.

7 more elements

A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:

receive a write command for writing a first amount of data to a memory device, the write command associated with a logical address;
read, based at least in part on the logical address, a first entry of a first logical-to-physical (L2P) table, wherein the first L2P table is for mapping a plurality of logical addresses to physical addresses of a corresponding first plurality of logical pages of the memory device that each have a first logical page size, and wherein the first entry of the first L2P table comprises a first physical address of a first logical page of the first plurality of logical pages;
identify, based at least in part on a size of the first amount of data, a second logical page size;
write, based at least in part on the first physical address, at least a portion of the first amount of data to a second logical page of the memory device having the second logical page size, the first logical page comprising the second logical page;
and
store, based at least in part on identifying the second logical page size, a first entry of a second L2P table for mapping a second plurality of logical addresses to physical addresses of a corresponding second plurality of logical pages of the memory device, each logical page of the second plurality of logical pages having the second logical page size, wherein the first entry in the second L2P table comprises a second physical address of the second logical page.

3 more elements

A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to:

receive a read command associated with a first logical address that is associated with a starting location of data stored in a memory device;
read a first entry of a first logical-to-physical (L2P) table based at least in part on the logical address, wherein the first entry comprises a first physical address of a first logical page of the memory device having a first logical page size, and wherein a value of a first portion of the first physical address indicates a second logical page size of a second logical page of memory that contains the data, the first logical page comprising the second logical page;
determine, based at least in part on the value of the first portion of the first physical address, whether the second logical page size is different than the first logical page size;
determine, based at least in part on the determination of whether the second logical page size is different than the first logical page size, a second physical address that points to the starting location of the data within the second logical page;
read the data from the starting location of the data within the second logical page based at least in part on the second physical address;
and
transmit the data to a host device for the memory device.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/117,907Filed 10 Dec 2020
Published: 16 Jun 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/1009
Address translation: using page tables, e.g. page table structures
G06F 2212/657
Details of virtual memory and virtual address translation: virtual address space management
G06F 2212/7201
Details relating to flash memory management: logical to physical mapping or translation of blocks or pages