Semiconductor memory apparatus, memory module, and memory system including memory module

A memory module comprising:

• J memory chips each including a plurality of unit memory areas and configured to input and output (input/output) data by accessing unit memory areas having sequence numbers, which do not overlap each other among the plurality of unit memory areas, in response to each of a plurality of translated address signals;
• and
• an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a row address signal included in a target address signal provided from an exterior of the memory module, to shift all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string, and to generate the plurality of translated address signals by adding second correction values to a unit area address included in the target address signal,
• wherein J represents the number of memory chips in the memory module, and
• wherein K represents a number.

A memory system comprising:

• a memory controller configured to generate a plurality of preliminary translated address signals by adding correction values to a target address signal, and to generate a plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string;
• and
• a memory module including J memory chips, configured to receive the plurality of translated address signals, and configured so that the J memory chips perform data input and output (input/output) with the memory controller in response to each of the plurality of translated address signals,
• wherein J represents the number of memory chips in the memory module, and
• wherein K represents a number.

A memory system comprising:

• a memory controller configured to generate a plurality of preliminary translated address signals by adding first correction values to a row address signal included in a target address signal, to shift all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string, and to generate the plurality of translated address signals by adding second correction values to a unit area address included in the target address signal;
• and
• a memory module including J memory chips each including a plurality of unit memory areas, and configured so that the J memory chips perform data input and output (input/output) with the memory controller by accessing unit memory areas having sequence numbers, which do not overlap each other among the plurality of unit memory areas, in response to each of the plurality of translated address signals,
• wherein J represents the number of memory chips in the memory module, and
• wherein K represents a number.

A semiconductor memory apparatus comprising:

• a memory area including J unit memory areas;
• a control circuit configured to generate a plurality of translated address signals by remapping a target address signal provided from an exterior of the memory module, and to output any one translated address signal corresponding to a unit area address included in the target address signal among the plurality of translated address signals;
• and
• an address decoder configured to decode the any one translated address signal and access the memory area according to a decoding result,
• wherein J represents the number of memory chips in the memory module, and
• wherein K represents a number.