Multi-tier cache for a memory system

An apparatus, comprising:

• a processor configured to:
• identify data for writing to a non-volatile memory, wherein the non-volatile memory comprises a first cache having a first set of memory cells operated as a first type of memory cell, a second cache having a second set of memory cells operated as a second type of memory cell, and a third set of memory cells operated as a third type of memory cell, and wherein the first cache and the second cache are caches for the third set of memory cells;
• select, from among a set of caches of the non-volatile memory that comprises the first cache and the second cache, a target cache for the data based at least in part on a characteristic of the data;
• and
• issue, to the non-volatile memory, a command to write the data to the target cache.

A system, comprising:

• a non-volatile memory comprising a first cache having a first set of memory cells operated as a first type of memory cell, a second cache having a second set of memory cells operated as a second type of memory cell, and a third set of memory cells operated as a third type of memory cell;
• and
• a host system coupled with the non-volatile memory, wherein the host system is configured to:
• identify data for writing to the non-volatile memory;
• select, from among a set of caches of the non-volatile memory that comprises the first cache and the second cache, a target cache for the data based at least in part on a characteristic of the data and
• issue, to the non-volatile memory, a command to write the data to the target cache.