US 2022/0188234 A1Published application

Storage device and operating method thereof

AssigneeSK hynix Inc.

InventorChung Un NA

Life of this patent

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Abstract

A storage device includes: a memory device including a plurality of planes, and a plurality of cache buffers and data buffers; and a memory controller for controlling the memory device to transmit first data and second data from first plane and second plane into the respective first cache buffer and second cache buffer, and control the first cache buffer and the second cache buffer to transmit the first data and the second data to the memory controller. In response to a read request for third data from a host while the first data is transmitting from the first cache buffer to the memory controller, the memory controller transmits a cache read command to the memory device such that the memory device reads the third data after the first data is completely transmitted to the memory controller, before the second data is transmitted from the second cache buffer.

Claims20

Dependent claims

A storage device comprising:

a memory device including a plurality of planes which is including a plurality of memory blocks storing data, and a plurality of pairs of cache buffers and data buffers, the pairs respectively coupled to the planes;
and
a memory controller configured to control the memory device to transmit first data and second data from first plane and second plane into the respective first cache buffer and second cache buffer, and configured to control the first cache buffer and the second cache buffer to transmit the first data to the memory controller when the first data and the second data are stored in the first cache buffer and the second cache buffer,
wherein, in response to a read request for third data from a host while the first data is transmitting from the first cache buffer to the memory controller, the memory controller is further configured to transmit a cache read command to the memory device such that the memory device reads the third data corresponding to the read request after the first data is completely transmitted from the first cache buffer to the memory controller, and before the second data is transmitted from the second cache buffer to the memory controller.

1 more element

A storage device comprising:

a memory device including a plurality of planes and a plurality of page buffers respectively corresponding to the plurality of planes;
and
a memory controller configured to control the memory device to perform a garbage collection operation of moving valid data included in each of the plurality of planes and a read operation of reading host data corresponding to a read request received from a host,
wherein, when the memory controller receives a read request for at least one plane from the host while the garbage collection operation is being performed on the plurality of planes, the memory controller is further configured to control the memory device to perform a cache read operation on the at least one plane in response to the read request for the at least one plane.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 17/358,922Filed 25 Jun 2021
Priority: KR 10-2020-017246910 Dec 2020
Published: 16 Jun 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

G06F 12/0246
Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory: in block erasable memory, e.g. flash memory
G06F 12/0844
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: multiple…
G06F 11/1068
In individual solid state devices: in sector programmable memories, e.g. flash disk
G06F 12/0253
Free address space management: garbage collection, i.e. reclamation of unreferenced memory