Managing cached data used by processing-in-memory instructions
AssigneeAdvanced Micro Devices, Inc.
InventorsJOHN KALAMATIANOS, JAGADISH B. KOTRA, GAGANDEEP PANWAR
Life of this patent
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Abstract
A system-on-chip configured for eager invalidation and flushing of cached data used by PIM (Processing-in-Memory) instructions includes: one or more processor cores; one or more caches and an I/O (input/output) die comprising logic to: receive a cache probe request, wherein the cache probe request including a physical memory address associated with a PIM instruction, and the PIM instruction is to be offloaded to a PIM device for execution; and issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device.
Claims20
A system-on-chip for eagerly invalidating and flushing cached data used by PIM (Processing-in-Memory) instructions comprising:
- one or more processor cores;
- one or more caches;
- and
- an I/O (input/output) die comprising logic to:
- receive a cache probe request, wherein the cache probe request includes a physical memory address associated with a PIM instruction, and the PIM instruction is to be offloaded to a PIM device for execution;
- and
- issue, based on the physical memory address, a cache probe to one or more of the caches prior to receiving the PIM instruction for dispatch to the PIM device.
A method of eagerly invalidating and flushing cached data used by PIM (Processing-in-Memory) instructions comprising:
- receiving a cache probe request, wherein the cache probe request includes a physical memory address associated with a PIM instruction, wherein the PIM instruction is to be offloaded to a PIM device for execution;
- and
- issuing a cache probe to one or more caches based on the physical memory address prior to receiving the PIM instruction for dispatch to the PIM device.
A method of eagerly invalidating and flushing cached data used by PIM (Processing-in-Memory) instructions, the method comprising:
- based on at least one first PIM instruction specifying a first physical memory address, speculating a second physical memory address;
- and
- issuing a cache probe to one or more caches before encountering a second PIM instruction that specifies the second physical memory address.
A system-on-chip for eagerly invalidating and flushing cached data used by PIM (Processing-in-Memory) instructions comprising:
- one or more processor cores;
- one or more caches;
- and
- an I/O (input/output) die comprising logic to:
- based on at least one first PIM instruction specify a first physical memory address, speculate a second physical memory address;
- and
- issue a cache probe to one or more caches before encountering a second PIM instruction that specifies the second physical memory address.
Dependencies are inferred from the claim text.