Low-bit density memory caching of parallel independent threads
AssigneeMicron Technology, Inc.
InventorLuca Bert
Life of this patent
Estimating the term…
Abstract
A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.
Claims20
A method comprising:
- programming a first data item to a first memory page of a first block included in a cache that resides in a first portion of a memory device, wherein the first data item is associated with a first processing thread;
- identifying a second memory page including a second data item associated with the first processing thread, wherein the second memory page is contained by a second block of the cache;
- copying the first data item and the second data item to a second portion of the memory device;
- and
- designating the first memory page and each of the one or more second memory pages as invalid.
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled to the memory device, the processing device to perform operations comprising:
- programming a first data item to a first memory page of a first block included in a cache that resides in a first portion of the memory device, wherein the first data item is associated with a first processing thread;
- identifying a second memory page including a second data item associated with the first processing thread, wherein the second memory page is contained by a second block of the cache;
- copying the first data item and the second data item to a second portion of the memory device;
- and
- designating the first memory page and each of the one or more second memory pages as invalid.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- programming a first data item to a first memory page of a first block included in a cache that resides in a first portion of a memory device, wherein the first data item is associated with a first processing thread;
- identifying a second memory page including a second data item associated with the first processing thread, wherein the second memory page is contained by a second block of the cache;
- copying the first data item and the second data item to a second portion of the memory device;
- and
- designating the first memory page and each of the one or more second memory pages as invalid.
Dependencies are inferred from the claim text.