US 2022/0188228 A1 · CACHE EVICTIONS MANAGEMENT IN A TWO LEVEL MEMORY CONTROLLER MODE

Abstract

Systems, apparatuses, and methods provide for a memory controller to manage cache evictions and/or insertions in a two level memory controller mode that uses a dynamic random access memory as a transparent cache for a persistent memory. For example, a memory controller includes logic to map cached data in the dynamic random access memory to an original address of copied data in the persistent memory. The cached data in the dynamic random access memory is tracked as to whether it is dirty data or clean data with respect to the copied data in the persistent memory. Upon eviction of the cached data from the dynamic random access memory, a writeback of the cached data that has been evicted to the persistent memory is bypassed when the cached data is tracked as dirty data.

Claims20

Dependent claims

A semiconductor apparatus comprising:

one or more substrates;
and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware logic, the logic to:
map, via a memory controller, cached data in a dynamic random access memory to an original address of copied data in a persistent memory, wherein the memory controller includes a two level memory controller mode that uses the dynamic random access memory as a transparent cache for the persistent memory;
track, via the memory controller, whether the cached data in the dynamic random access memory is valid or invalid data with respect to the copied data in the persistent memory;
evict, via the memory controller, the cached data from the dynamic random access memory;
and
bypass, via the memory controller, a writeback of the cached data that has been evicted to the persistent memory when the cached data is tracked as invalid data.

5 more elements

A storage device comprising:

a tiered memory including a dynamic random access memory and a persistent memory;
and
a memory controller coupled to the tiered memory, the memory controller to:
map cached data in the dynamic random access memory to an original address of copied data in the persistent memory, wherein the memory controller includes a two level memory controller mode that uses the dynamic random access memory as a transparent cache for the persistent memory;
track whether the cached data in the dynamic random access memory is valid or invalid data with respect to the copied data in the persistent memory;
evict the cached data from the dynamic random access memory;
and
bypass a writeback of the cached data that has been evicted to the persistent memory when the cached data is tracked as invalid data.

5 more elements

At least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:

map, via a memory controller of a memory device, cached data in a dynamic random access memory to an original address of copied data in a persistent memory, wherein the memory controller includes a two level memory controller mode that uses the dynamic random access memory as a transparent cache for the persistent memory;
track, via the memory controller, whether the cached data in the dynamic random access memory is valid or invalid data with respect to the copied data in the persistent memory;
evict, via the memory controller, the cached data from the dynamic random access memory;
and
bypass, via the memory controller, a writeback of the cached data that has been evicted to the persistent memory when the cached data is tracked as invalid data.

2 more elements

Dependencies are inferred from the claim text.

Cache evictions management in a two level memory controller mode

Life of this patent

Cache evictions management in a two level memory controller mode

Life of this patent

Abstract

Claims20