Hierarchical task scheduling for accelerators

A chipset comprising:

• first circuitry configured to implement a task scheduler;
• and
• second circuitry, distinct from and coupled to the first circuitry, incorporating a processor core and implementing an accelerator and a sub-task scheduler;
• wherein the first circuitry is configured to dispatch a first task to the second circuitry based on output from the task scheduler;
• and
• wherein the sub-task scheduler is configured to schedule a plurality of sub-tasks of the first task for execution at the accelerator.

A computer-implemented method comprising:

• producing a first computer-readable description of first circuitry implementing a task scheduler;
• producing a second computer-readable description of second circuitry, distinct from and coupled to the first circuitry, incorporating a processor core and implementing a sub-task scheduler;
• wherein the first circuitry is configured to dispatch a first task to the second circuitry based on output from the task scheduler and the sub-task scheduler is configured to schedule a plurality of sub-tasks of the first task at an accelerator;
• and
• storing the first and second computer-readable descriptions in one or more computer-readable storage media, the first and second computer-readable descriptions being usable for fabricating one or more masks or reticles for manufacturing one or more integrated circuits implementing the first circuitry and the second circuitry.