Computational array microprocessor system with variable latency memory access
AssigneeTesla, Inc.
InventorsEmil Talpes, Peter Joseph Bannon, Kevin Altair Hurd
Life of this patent
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Abstract
A microprocessor system comprises a computational array and a hardware arbiter. The computational array includes a plurality of computation units. Each of the plurality of computation units operates on a corresponding value addressed from memory. The hardware arbiter is configured to control issuing of at least one memory request for one or more of the corresponding values addressed from the memory for the computation units. The hardware arbiter is also configured to schedule a control signal to be issued based on the issuing of the memory requests.
Claims22
-21. (canceled)
A microprocessor system, comprising:
- a computational array that includes a plurality of computation units, wherein each of the plurality of computation units operates on a corresponding value addressed from memory;
- and
- a hardware arbiter configured to manage memory requests, wherein the hardware arbiter is in communication with a control queue configured to queue operations, and wherein the hardware arbiter is configured to trigger an operation of one or more computation units in the plurality of computation units on a subset of the corresponding values based on the hardware arbiter granting memory access for the subset of the corresponding values.
A method implemented by a microprocessor system, the method comprising:
- receiving an operation for a computational array, wherein the hardware computational array includes a hardware arbiter and a plurality of computation units, and wherein each of the plurality of computation units operates on a corresponding value addressed from memory;
- causing, by the hardware arbiter, one or more memory requests associated with the operation to be queued in a control queue, the memory requests being for a subset of the corresponding values;
- and
- triggering, by the hardware arbiter using a control signal, the operation based on granting of the one or more memory requests, wherein the control signal triggers the control queue to release the operation.
Dependencies are inferred from the claim text.