Pipeline Protection for CPUs With Save and Restore of Intermediate Results

A device comprising:

• a set of pipelines that each include a respective set of functional units;
• for each pipeline of the set of pipelines, a respective capture queue;
• and
• a scoreboard circuit coupled to the set of pipelines and to the respective capture queues and configured to, for each pipeline of the set of pipelines, based on a hazard associated with the respective pipeline of the set of pipelines:
• cause the respective pipeline to stall an instruction associated with the hazard by causing the respective capture queue to store an intermediate result of the instruction;
• permit the pipeline to execute a subsequent instruction while the instruction is stalled;
• and
• after the hazard is resolved, cause the respective pipeline to resume the instruction by causing the intermediate result to be restored to the respective pipeline.

A method comprising:

• receiving a first instruction, a second instruction, and a third instruction;
• beginning execution of the first instruction by a processor pipeline having a set of functional units;
• beginning execution of the second instruction by the processor pipeline to produce an intermediate result;
• detecting a hazard with respect to the second instruction based on the first instruction;
• based on the hazard, stalling the second instruction by storing the intermediate result in a capture queue;
• while the second instruction is stalled:
• beginning execution of the third instruction by the processor pipeline;
• and
• completing execution of the first instruction;
• and
• resuming execution of the second instruction by restoring the intermediate result to the processor pipeline.