Arithmetic processing circuit and arithmetic processing method

An arithmetic processing circuit, comprising:

• an instruction fetch address generating unit configured to generate fetch addresses successively such that a plurality of instructions are included in one fetch line;
• an address table configured to store a branch destination address and a first tag for each of a plurality of indexes, the indexes being defined as a first bit string that is extracted from a fetch address by including at least one bit among instruction address bits whose values vary within the one fetch line, the first tag being a second bit string situated at higher bit positions than the first bit string in the fetch address;
• an upper tag storage unit configured to store a second tag, which is a third bit string situated at higher bit positions than the first tag among a plurality of bits constituting the fetch address;
• and
• a branch direction determination unit configured to supply to the instruction fetch address generating unit the branch destination address retrieved from the address table in response to the fetch address, upon determining that the first tag retrieved from the address table in response to the fetch address and the second tag stored in the upper tag storage unit match respective portions of the fetch address.