Stream reference register with double vector and dual single vector operating modes

A data processing device comprising:

• an instruction memory to store instructions;
• an instruction decoder to decode an instruction recalled from the instruction memory;
• a plurality of functional units, each functional unit being operable to perform a data processing operation in response to an operand specified by an instruction decoded by the instruction decoder;
• and
• stream data logic operable to recall data streams from a memory, wherein each data stream includes a sequence of data elements, wherein the stream data logic includes:
• a stream data unit that includes:
• a data buffer having an input side and an output side, wherein the input side coupled to a memory interface of the stream data logic to receive data elements from the memory;
• a first stream head register coupled to the output side of the data buffer to receive a first data element from the data buffer;
• a second stream head register coupled to the output side of the data buffer to receive a second data element from the data buffer, wherein the first and second data elements are sequential data elements within a first data stream;
• and
• an output bus coupled to the first and second stream head registers;
• wherein said instruction decoder is operable to:
• when the operand of the recalled instruction specifies a first bit coding, cause the first data element to be output from the first stream head register to one of the functional units on the output bus but not cause the second data element to be output from the second stream head register;
• when an operand of the recalled instruction specifies a second bit coding, cause the second data element to be output from the second stream head register to one of the functional units on the output bus but not cause the first data element to be output from the first stream head register;
• and
• when an operand of the recalled instruction specifies a third bit coding, cause the first data element to be output from the first stream head register to one of the functional units and the second data element to be output from the second stream head register to one of the functional units on the output bus.