US 2022/0188114 A1Published application

Apparatuses, methods, and systems for hashing instructions

AssigneeIntel Corporation

InventorsRegev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described. In one embodiment, a processor includes a decode circuit to decode a single instruction into a decoded single instruction, the single instruction including at least one first field that identifies eight 32-bit state elements A, B, C, D, E, F, G, and H for a round according to a SM3 hashing standard and at least one second field that identifies an input message; and an execution circuit to execute the decoded single instruction to: rotate state element C left by 9 bits to form a rotated state element C, rotate state element D left by 9 bits to form a rotated state element D, rotate state element G left by 19 bits to form a rotated state element G, rotate state element H left by 19 bits to form a rotated state element H, perform two rounds according to the SM3 hashing standard on the input message and state element A, state element B, rotated state element C, rotated state element D, state element E, state element F, rotated state element G, and rotated state element H to generate an updated state element A, an updated state element B, an updated state element E, and an updated state element F, and store the updated state element A, the updated state element B, the updated state element E, and the updated state element F into a location specified by the single instruction.

Claims20

Dependent claims

A processor comprising:

a decode circuit to decode a first instruction, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element and a sixth 64-bit data element;
and
an execution circuit coupled with the decode circuit, the execution circuit to perform operations corresponding to the first instruction, including to:
generate a result, the result to include:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits;
and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits;
and
store the result in the first vector register.

8 more elements

A method comprising:

decoding a first instruction, the first instruction comprising a plurality of fields specifying a first vector register and a second vector register, the first vector register storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register storing a fifth 64-bit data element and a sixth 64-bit data element;
and
performing operations corresponding to the first instruction, including:
generating a result, the result including:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits;
and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits;
and
storing the result in the first vector register.

8 more elements

A system comprising:

a non-transitory machine readable storage medium storing code that when executed by the system causes the system to convert a first instruction of a first instruction set into one or more instructions of a second, different instruction set, the first instruction comprising a plurality of fields to specify a first vector register and a second vector register, the first vector register to store a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register to store a fifth 64-bit data element and a sixth 64-bit data element;
a processor coupled with the non-transitory machine readable storage medium, the processor to perform the one or more instructions of the second instruction set to perform operations corresponding to the first instruction, including to:
generate a result, the result to include:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits;
and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits;
and
store the result in a destination.

7 more elements

A non-transitory machine readable storage medium storing code, including a first instruction, that when executed by a machine causes the machine to perform a method comprising:

decoding the first instruction, the first instruction comprising a plurality of fields specifying a first vector register and a second vector register, the first vector register storing a first 64-bit data element, a second 64-bit data element, a third 64-bit data element, and a fourth 64-bit data element, the second vector register storing a fifth 64-bit data element and a sixth 64-bit data element;
and
performing operations corresponding to the first instruction, including:
generating a result, the result including:
a first 64-bit result element that is to be equivalent to the first 64-bit data element added to a value equivalent to the fifth 64-bit data element rotated right by nineteen bits exclusive OR'd (XOR'd) with the fifth 64-bit data element rotated right by sixty-one bits XOR'd with the fifth 64-bit data element shifted right by six bits;
a second 64-bit result element that is to be equivalent to the second 64-bit data element added to a value equivalent to the sixth 64-bit data element rotated right by nineteen bits XOR'd with the sixth 64-bit data element rotated right by sixty-one bits XOR'd with the sixth 64-bit data element shifted right by six bits;
a third 64-bit result element that is to be equivalent to the third 64-bit data element added to a value equivalent to the first 64-bit result element rotated right by nineteen bits XOR'd with the first 64-bit result element rotated right by sixty-one bits XOR'd with the first 64-bit result element shifted right by six bits;
and
a fourth 64-bit result element that is to be equivalent to the fourth 64-bit data element added to a value equivalent to the second 64-bit result element rotated right by nineteen bits XOR'd with the second 64-bit result element rotated right by sixty-one bits XOR'd with the second 64-bit result element shifted right by six bits;
and
storing the result in a destination.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/688,728Filed 7 Mar 2022
Priority: 29 Mar 2019
Published: 16 Jun 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 9/30007
Arrangements for executing specific machine instructions: to perform operations on data operands
G06F 9/30145
Arrangements for executing machine instructions, e.g. instruction decode: instruction analysis, e.g. decoding, instruction word fields
G06F 9/30036
To perform operations on data operands: instructions to perform operations on packed data, e.g. vector, tile or matrix operations
G06F 9/30038
Instructions to perform operations on packed data, e.g. vector, tile or matrix operations: using a mask

Family

Application16/370,459Continuation · filed 29 Mar 2019
Application17/087,536Continuation · filed 2 Nov 2020
Application17/537,373Continuation · filed 29 Nov 2021
Application17/688,728Continuation
US 10,824,428 B2Related patent
US 11,188,335 B2Related patent
US 11,567,772 B2Related patent
US 11,681,530 B2Related patent
US 2020/0310802 A1Published application
US 2021/0049013 A1Published application
US 2022/0147356 A1Published application
US 2022/0188114 A1This patent

From the US filing history. Foreign family members aren’t listed.