Dual vector arithmetic logic unit
AssigneeAdvanced Micro Devices, Inc.
InventorsBin He, Brian Emberling, Mark Leather, Michael Mantor
Life of this patent
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Abstract
A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.
Claims20
A method comprising:
- storing, at a cache, a set of wavefronts, each wavefront comprising a number of work items, for execution at an execution unit comprising a first arithmetic unit (ALU) pipeline and a second ALU pipeline;
- and
- selectively executing either a single instruction or a dual instruction on the set of wavefronts in a first execution cycle both at the first ALU pipeline and at the second ALU pipeline.
A method, comprising:
- selectively executing either a single instruction or a dual instruction, both at a first arithmetic logic unit (ALU) pipeline comprising a plurality of ALUs and at a second ALU pipeline comprising a plurality of ALUs, in a first execution cycle based on a set of wavefronts stored at a cache, wherein a first wavefront of the set of wavefronts comprises a number of work items equal to a number of ALUs in the first ALU pipeline plus a number of ALUs in the second ALU pipeline.
A device, comprising:
- a cache to store a first set of wavefronts, each wavefront comprising a number of work items;
- and
- an execution unit comprising a first arithmetic unit (ALU) pipeline and a second ALU pipeline to selectively execute either a single instruction or a dual instruction on the first set of wavefronts in a first execution cycle both at the first ALU pipeline and at the second ALU pipeline, wherein the first ALU pipeline and the second ALU pipeline each comprise a plurality of ALUs.
Dependencies are inferred from the claim text.