Data-type-aware clock-gating

An integrated circuit device comprising:

• a data register configured to store a numeric value that supports a plurality of data types;
• a first clock-gate circuit configured to clock-gate a first portion of the data register independently from rest of the data register, the first portion of the data register storing a first group of data bits that are unused for a data type of the plurality of data types;
• and
• a second clock-gate circuit configured to clock-gate a second portion of the data register independently from rest of the data register, the second portion of the data register storing a second group of data bits that have a constant value for numeric values within a numeric range.

A method comprising:

• receiving a first numeric value;
• storing the first numeric value in a data register that supports a plurality of data types;
• receiving a second numeric value;
• and
• in response to receiving the second numeric value:
• determining that a portion of the data register is storing a value that is equal to a group of data bits of the second numeric value being inputted into the portion of the data register,
• wherein the group of data bits are unused in a data type of the plurality of data types, or the group of data bits have a constant value for numeric values within a numeric range;
• and
• disabling a clock input signal to the portion of the data register.