Memory access

An apparatus for triggering prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system, the apparatus comprising:

• first circuitry for obtaining command data from one or more memory access commands in a sequence of memory access commands for the memory access component;
• second circuitry for predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more memory access requests, from the obtained command data;
• and
• third circuitry for, in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.

A data processing system comprising:

• a processor;
• a memory management function;
• and
• storage accessible by the processor via the memory management function,
• wherein the processor is configured to trigger prefetching of memory address translations, for memory access requests to be issued by the processor to the memory management function, by:
• obtaining instruction data from a sequence of instructions;
• predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more predicted memory access requests, from the obtained instruction data;
• and
• in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.