Memory with virtual page size
AssigneeMicron Technology, Inc.
InventorDean D. Gans
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.
Claims21
(canceled)
A method, comprising:
- receiving a request to access one or more memory cells of a memory array;
- sending a first command to identify a set of memory cells of the memory array based at least in part on the request, wherein the set of memory cells comprises a first quantity of memory cells corresponding to a nominal page size of the memory array;
- sending one or more second commands to activate a first subset of the set of memory cells and a second subset of the set of memory cells, wherein the first subset and the second subset each comprise a second quantity of memory cells corresponding to an internal page size of the memory array;
- and
- accessing at least one memory cell of the first subset and at least one memory cell of the second subset in response to the request.
An electronic memory apparatus, comprising:
- a memory array that includes a plurality of row access lines that are each coupled with a row of memory cells of the memory array and a plurality of column access lines that are each coupled with a column of memory cells of the memory array;
- and
- a memory controller coupled with the plurality of row access lines and the plurality of column access lines, wherein the memory controller is operable to:
- receive a request to access one or more memory cells of the memory array;
- send a first command to identify a set of memory cells of the memory array based at least in part on the request, wherein the set of memory cells comprises a first quantity of memory cells corresponding to a nominal page size of the memory array;
- send one or more second commands to activate a first subset of the set of memory cells and a second subset of the set of memory cells, wherein the first subset and the second subset each comprise a second quantity of memory cells corresponding to an internal page size of the memory array;
- and
- access at least one memory cell of the first subset and at least one memory cell of the second subset in response to the request.
An apparatus, comprising:
- means for receiving a request to access one or more memory cells of a memory array;
- means for sending a first command to identify a set of memory cells of the memory array based at least in part on the request, wherein the set of memory cells comprises a first quantity of memory cells corresponding to a nominal page size of the memory array;
- means for sending one or more second commands to activate a first subset of the set of memory cells and a second subset of the set of memory cells, wherein the first subset and the second subset each comprise a second quantity of memory cells corresponding to an internal page size of the memory array;
- and
- means for accessing at least one memory cell of the first subset and at least one memory cell of the second subset in response to the request.
Dependencies are inferred from the claim text.