Semiconductor memory device and test system including the same

A semiconductor memory device, comprising:

• a command and address generator, the command and address generator being configured to, during a test operation:
• generate a register address together with a register write command, generate a row address together with a test active command, or generate a column address together with a test write command by receiving and decoding a test command/address in response to a test clock signal, or
• generate the column address and a test pattern data selection signal together with a test read command by receiving and decoding the test command/address and a special-purpose signal in response to the test clock signal;
• a test pattern data storage, the test pattern data storage being configured to, during the test operation:
• store test write pattern data in response to the register write command and the register address, wherein each test write pattern data has a first predetermined number of bits, and
• output test read pattern data in response to the test read command and the test pattern data selection signal, wherein each test read pattern data has the first predetermined number of bits;
• a row decoder, which generates a word line selection signal by decoding the row address;
• a column decoder, which generates a column selection signal by decoding the column address;
• a memory cell array, which outputs data from memory cells selected by the word line selection signal and the column selection signal;
• a test write data generation unit, the test write data generation unit being configured to, during the test operation:
• copy, or invert and copy, a number n of test write data at a first data rate in response to a test write clock signal, wherein each of the test write data has a second predetermined number of bits, and
• generate n write data at a second data rate, wherein the second data rate is higher than the first data rate, and wherein each of the write data has the first predetermined number of bits;
• a write path unit, the write path unit being configured to parallelize the n write data;
• a read path unit, the read path unit being configured to serialize the data output from the memory cell array to generate n read data, wherein each of the n read data has the first predetermined number of bits;
• and
• a test read data generation unit, the test read data generation unit being configured to, during the test operation:
• generate n test read data by comparing the test read pattern data with each of the n read data at the first data rate, wherein the comparing is performed on a basis of a third predetermined number of bits, and wherein each of the n test read data has a fourth predetermined number of bits, and
• generate the n test read data at a third data rate, wherein the third data rate is lower than the first data rate.

A test system, comprising:

• a test apparatus, the test apparatus being configured to:
• apply a test command/address in response to a test clock signal,
• transmit test data or test write pattern data having a first predetermined number of bits in response to a test write clock signal, and
• receive the test data;
• and
• a semiconductor memory device, the semiconductor memory device including:
• a test pattern data storage, the test pattern data storage being configured to, during a test operation:
• store test write pattern data in response to a register address when the test command/address is a register write command and the register address, wherein each of the test write pattern data has the first predetermined number of bits, and
• output test read pattern data in response to a test pattern data selection signal when the test command/address is a test read command and the test pattern data selection signal, wherein each of the test read pattern data has the first predetermined number of bits;
• a row decoder, which generates a word line selection signal by decoding a row address;
• a column decoder, which generates a column selection signal by decoding a column address;
• a memory cell array, which outputs data from memory cells selected by the word line selection signal and the column selection signal;
• a read path unit, the read path unit being configured to serialize the data output from the memory cell array to generate n read data, wherein each of the n read data has the first predetermined number of bits;
• and
• a test read data generation unit, the test read data generation unit being configured to, during the test operation:
• generate n test read data by comparing the test read pattern data with each of the n read data at a first data rate, wherein the comparing is performed on a basis of a second predetermined number of bits, and wherein each of the n test read data has a third predetermined number of bits, and
• generate the n test read data at a second data rate, wherein the second data rate is lower than the first data rate.