Refresh management for dram

A method, comprising:

• selectively placing memory commands in a memory interface queue and transmitting the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM);
• maintaining an activate counter related to a number of activate commands sent over the memory channel to a memory region of the DRAM;
• in response to the activate counter being at or above a designated threshold, signaling an arbiter that a refresh command should be sent to the memory region;
• and
• in response to a designated condition, adjusting a value of the activate counter by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.

A data processing system, comprising:

• a data processor;
• a data fabric coupled to the data processor;
• and
• a memory controller coupled to the data fabric for fulfilling memory requests from the data processor, the memory controller comprising:
• a memory interface queue having an output coupled to a memory channel adapted for coupling to at least one dynamic random access memory (DRAM);
• an arbiter coupled to the memory interface queue for selecting memory commands and placing them in the memory interface queue to be transmitted over the memory channel;
• a refresh control circuit coupled to the arbiter and operable to monitor an activate counter which maintains a count related to a number of activate commands sent over the memory channel to a memory region, and in response to the activate counter being above a designated threshold, signal the arbiter that a refresh command should be sent to the memory region;
• and
• an activate counter adjustment circuit coupled to the activate counter and operable to respond to a designated condition by adjusting a value of the activate counter by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.