Memory system and electronic system including the same

A memory system comprising:

• a memory controller configured to control an operation of a memory cell array by providing a command/address through a first command/address pin and a second command/address pin different from the first command/address pin, perform training on a first command/address signal transmitted through the first command/address pin based on a first time, and perform training on a second command/address signal transmitted through the second command/address pin based on the first time;
• and
• a memory device configured to receive the trained first and second command/address signals and include a plurality of data pins which output first command/address data and second command/address data respectively corresponding to the first and second command/address signals,
• wherein the memory device outputs the first and second command/address data through a first data pin among the plurality of data pins.

An electronic system comprising:

• a host configured to provide a command for requesting an input or output of data;
• a memory controller configured to control an operation of a memory cell array by providing a command/address through a first command/address pin and a second command/address pin different from the first command/address pin;
• and
• a memory device including a plurality of data pins configured to provide the data of the memory cell array input or output through the command/address to the memory controller,
• wherein the memory device further includes:
• a first flip-flop configured to sample a first command/address signal provided through the first command/address pin, as first command/address data at a first time;
• and
• a second flip-flop configured to sample a second command/address signal provided through the second first command/address pin, as second command/address data at the first time, and
• wherein the first and second command/address data is provided to the memory controller through a first data pin among the plurality of data pins.