Memory device, data outputing method thereof, and memory system having the same

A memory device, comprising:

• a memory cell array;
• a plurality of transceivers configured to transmit/receive data of the memory cell array through data lines by a multilevel signaling method;
• a data bus inversion (DBI) transceiver configured to transmit/receive DBI data by the multilevel signaling method through a data bus inversion line;
• and
• a cyclic redundancy check (CRC) transceiver configured to transmit/receive CRC values of the data by the multilevel signaling method through an error detection check (EDC) line, wherein:
• the memory device is configured to separate the data into a plurality of sub-data, generate the CRC values corresponding to each of the plurality of sub-data, and order the CRC values, and
• the CRC transceiver includes a transmitter configured to transmit the ordered CRC values by the multilevel signaling method.

A data output method of a memory device, the method comprising:

• separating data that is read from a memory cell array into a plurality of sub-data;
• calculating cyclic redundancy check (CRC) values corresponding to the plurality of sub-data, respectively;
• ordering the calculated CRC values;
• and
• transmitting the ordered CRC values along with the data by a multilevel signaling method.