US 2022/0188001 A1 · TECHNIQUES FOR MAPPING MEMORY ALLOCATION TO DRAM DIES OF A STACKED MEMORY MODULE

Abstract

Methods and apparatus for mapping memory allocation to DRAM dies of a stacked memory modules are described herein. Memory address ranges in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies are mapped to DRAM dies in the module based on a layer of the DRAM dies, where dies in different layers have different thermal dissipation characteristic. Chunks of the memory address range are allocated to software entities such as virtual machines (VMs) and/or applications based on a memory access rate of the VMs/applications and the thermal dissipation characteristics of the DRAM die layers, wherein VMs/applications with higher memory access rate are allocated memory on DRAM dies with higher thermal dissipation. In one aspect, memory ranks are associated with respective die layers. In response to detection of change in access rates, memory may be migrated between ranks. Interleaving at multiple levels is also supported.

Claims20

Dependent claims

A method for allocating memory in a module employing 3DS (three dimensional stacked) DRAMs (Dynamic Random Access Memories) comprising stacked DRAM dies, comprising:

mapping memory address ranges to DRAM dies in the module based at least on a layer of the DRAM dies and thermal dissipation characteristics of the DRAM die layers.

A compute system, comprising:

a plurality of 3DS (three dimensional stacked) DRAM (Dynamic Random Access Memory) DIMMs (Dual In-line Memory Modules), each having a plurality of DRAM devices having a stacked DRAM die structure;
a central processing unit (CPU) having one or more memory controllers coupled to the plurality of 3DS DRAM DIMMs;
BIOS firmware, stored in a storage device in the system and configured to be executed on the CPU to enable the compute system to:
associate DRAM dies in respective layers in the 3DS DRAM devices with respective memory ranks;
and
assign address ranges in a system memory map to the plurality of memory ranks.

3 more elements

One or more non-transitory machine-readable mediums having instructions stored thereon configured to be executed on a central processing unit (CPU) of a compute system including a plurality of 3DS (three dimensional stacked) DRAM (Dynamic Random Access Memory) DIMMs (Dual In-line Memory Modules), each having a plurality of DRAM devices having a stacked DRAM die structure, the CPU having one or more memory controllers coupled to the plurality of 3DS DRAM DIMMs, wherein execution of the instructions enables the compute system to:

map memory address ranges to DRAM dies in the plurality of 3DS DRAM DIMMs based at least on a layer of the DRAM dies and thermal dissipation characteristics of the DRAM die layers.

Dependencies are inferred from the claim text.

Techniques for mapping memory allocation to dram dies of a stacked memory module

Life of this patent

Techniques for mapping memory allocation to dram dies of a stacked memory module

Life of this patent

Abstract

Claims20