Managing dielectric stress of a memory device using controlled ramping slopes
AssigneeMicron Technology, Inc.
InventorsSheyang Ning, Lawrence Miranda
Life of this patent
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Abstract
Control logic in a memory device identifies a request to execute a memory access operation on the memory cell. A first set of pulses corresponding to a first voltage ramp slope level is caused to be applied to the memory cell during a first time interval of the memory access operation. The control logic causes a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
Claims20
A memory device comprising:
- a memory array comprising a memory cell;
- and
- control logic, operatively coupled with the memory array, to perform operations comprising:
- identifying a request to execute a memory access operation on the memory cell;
- causing a first set of pulses corresponding to a first voltage ramp slope level to be applied to the memory cell during a first time interval of the memory access operation;
- and
- causing a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising:
- receiving a request to execute a program operation on a memory cell;
- and
- causing a plurality of sets of programming pulses to be applied to the memory cell to ramp the memory cell to a wordline voltage level during execution of the program operation, wherein each of plurality of sets of programming pulses corresponds to a different slope level.
A method comprising:
- identifying, by a processing device, a request to execute a memory access operation on the memory cell;
- causing a first set of pulses corresponding to a first voltage ramp slope level to be applied to the memory cell during a first time interval of the memory access operation;
- and
- causing a second set of pulses corresponding to a second voltage ramp slope level to be applied to the memory cell during a second time interval of the execution of the memory access operation, wherein the first slope level and the second slope level are different.
Dependencies are inferred from the claim text.