US 2022/0187369 A1 · METHOD AND APPARATUS FOR DEBUGGING INTEGRATED CIRCUIT SYSTEMS USING SCAN CHAIN

Abstract

A circuit debug apparatus for debugging an integrated circuit that causes a functional fault may include a processor configured to extract a scan pattern of a scan chain of the integrated circuit while the integrated circuit is in a scan mode. The scan pattern includes a plurality of logic states for a corresponding plurality of logic circuits of the integrated circuit. The processor may also be configured to apply a modified scan pattern to the integrated circuit while the integrated circuit is in the scan mode, where the modified scan pattern includes a test pattern configured to eliminate the functional fault. The processor may be further configured to determine whether the integrated circuit with the modified scan pattern produces the functional fault while the integrated circuit is in a functional mode.

Claims20

Dependent claims

A method of debugging an integrated circuit that causes a functional fault while the integrated circuit is in a functional mode, the method comprising:

extracting, while the integrated circuit is in a scan mode, a scan pattern of a scan chain of the integrated circuit captured at the time of the functional fault, the scan pattern comprising a plurality of logic states for a corresponding plurality of logic circuits that define the scan chain;
testing a test pattern to determine if the test pattern does not result in the functional fault, the testing comprising:
causing the integrated circuit to enter the scan mode;
inputting the test pattern into the scan chain;
causing the integrated circuit to enter the functional mode after the inputting of the test pattern;
and
determining if the test pattern does not result in the functional fault;
and
responsive to the test pattern resulting in the functional fault, repeating the testing with a different test pattern.

6 more elements

A circuit debug apparatus for debugging an integrated circuit that causes a functional fault while the integrated circuit is in a functional mode, the apparatus comprising:

a processor configured to:
extract a scan pattern of a scan chain of the integrated circuit while the integrated circuit is in a scan mode, the scan pattern comprising a plurality of logic states for a corresponding plurality of logic circuits of the integrated circuit captured at the time of the functional fault;
test a modified scan pattern to determine if the modified scan pattern does not produce the function fault, wherein the modified scan pattern includes a test pattern and the processor tests a modified scan pattern by being further configured to:
cause the integrated circuit to enter the scan mode;
apply the modified scan pattern to the integrated circuit;
and
cause the integrated circuit to enter the functional mode after applying the modified scan pattern;
and
determine whether the integrated circuit with the modified scan pattern produces does not produce the functional fault;
and
repeat the test with a different modified scan pattern in response to the modified scan pattern producing the functional fault.

8 more elements

Dependencies are inferred from the claim text.

Method and apparatus for debugging integrated circuit systems using scan chain

Life of this patent

Method and apparatus for debugging integrated circuit systems using scan chain

Life of this patent

Abstract

Claims20