Memory device detecting defect by measuring line resistance of word line
AssigneeSamsung Electronics Co., Ltd.
InventorsHWANGJU SONG, JAEEUN YOON, JISEOK LEE, SANGWON HWANG
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Abstract
A memory device includes; a memory cell array including memory cells, a row decoder selecting a word line in response to a received address, and control logic including a sensing capacitor having a size proportional to a size of a word line capacitor associated with the selected word line. The control logic measures line resistance of the selected word line by precharging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor following the precharging of the selected word line, and measuring a voltage of the sensing capacitor following the performing of the charge sharing operation.
Claims20
A memory device comprising:
- a memory cell array including memory cells respectively arranged in regions wherein word lines and bit lines intersect;
- a row decoder configured to select a word line (“the selected word line”) from among the word lines in response to a received address;
- and
- control logic including a sensing capacitor having a size proportional to a size of a word line capacitor associated with the selected word line,
- wherein the control logic is configured to measure line resistance of the selected word line by precharging the selected word line, performing a charge sharing operation between the selected word line and the sensing capacitor following the precharging of the selected word line, and measuring a voltage of the sensing capacitor following the performing of the charge sharing operation.
A memory device comprising:
- a memory cell array including memory cells respectively arranged in regions wherein word lines and bit lines intersect;
- a row decoder configured to select one word line (“the selected word line”) from among the word lines in response to a received address;
- and
- control logic configured to measure line resistance of the selected word line, wherein the control logic includes:
- a sensing capacitor;
- a voltage driver providing a charge voltage;
- a first switch having a first end connected to the voltage driver and a second end;
- a second switch having a first end connected to the selected word line and a second end connected to the second end of the first switch;
- a third switch having a first end connected between the first switch and the second switch and a second end;
- a fourth switch connected in parallel with the sensing capacitor and connected to the second end of the third switch;
- and
- a comparator including a first input terminal receiving a sense voltage from the sensing capacitor and a second input terminal receiving a reference voltage.
A memory device comprising:
- a memory cell array including memory cells respectively arranged in regions wherein word lines and bit lines intersect;
- a row decoder configured to select a word line (“the selected word line”) from among the word lines in response to a received address;
- and
- control logic including a normal unit configured to perform at least one data access operation in relation to a memory cell connected to the selected word line, and a test unit including a sensing capacitor,
- wherein the test unit is configured to measure line resistance of the selected word line and measure leakage current associated with the selected word line by
- performing a charge sharing operation between the selected word line and the sensing capacitor,
- measuring a voltage of the sensing capacitor during a first time period following the performing of the charge sharing operation to measure the line resistance of the selected word line, and
- measuring the voltage of the sensing capacitor during a second time period following the first time period to measure the leakage current associated with the selected word line.
Dependencies are inferred from the claim text.