Analog receiver equalizer architectures for high-speed wireline and optical application

A receiver comprising:

• an interleaver configured to receive an input signal and to provide time-interleaved outputs by providing a time delay between the time-interleaved outputs;
• a plurality of slices connected to an output end of the interleaver, the plurality of slices configured to respectively process the time-interleaved outputs using a respective clock for each slice, each of the slices comprising an equalizer to equalize a respective one of the time-interleaved outputs and a sampler to sample an output of the equalizer to detect data in the respective one of the time-interleaved outputs;
• and
• a processor configured to control the equalizer in each of the slices based on feedback from the respective sampler in each slice among the slices and to adapt the equalizer in a first one of the slices independently of equalizers in the other slices by decoupling a contribution from the sampler of the first one of the slices to de-skew the clock of the first one of the slices.