Test devices, test systems, and operating methods of test systems

A test system, comprising:

• a test board configured to communicate with a test device, the test device including a non return to zero (NRZ) interface circuit,
• wherein the test board is configured to
• receive a first NRZ signal having a voltage level according to a logic state of a first bit among multiple bits from the test device via a first channel, and
• receive a second NRZ signal having a voltage level according to a logic state of a second bit among the multiple bits from the test device via a second channel,
• wherein the test board includes a superposition line configured to provide a pulse amplitude modulation (PAM) signal, which is generated to satisfy a PAM operation based on voltage-superposing the first NRZ signal and the second NRZ signal, as a test signal to a device under test (DUT).

An operation method of a test system configured to test a device under test (DUT) performing an interface of a pulse amplitude modulation (PAM) operation, the operation method comprising:

• outputting a first non return to zero (NRZ) signal according to a logic state of a first bit among multiple bits corresponding to a test pattern via a first channel;
• outputting a second NRZ signal according to a logic state of a second bit among the multiple bits via a second channel;
• and
• providing a PAM signal generated to satisfy the PAM operation based on voltage-superposing the first NRZ signal and the second NRZ signal as a test signal to the DUT,
• wherein the first NRZ signal has a first high level or a first low level according to the logic state of the first bit, and the second NRZ signal has a second high level or a second low level according to the logic state of the second bit,
• wherein the first high level is different from the second high level.