Apparatus and methods for low power frequency clock generation and distribution
AssigneeCiena Corporation
InventorsMahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson
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Abstract
Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.
Claims20
A device comprising:
- a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2;
- and
- a differential frequency doubler configured to
- generate a single-ended multiplied frequency clock from the differential FS/N frequency clock;
- and
- convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.
A method for low power clock generation and distribution, the method comprising:
- generating, by a clock generation circuit of a data processing device, a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2;
- distributing, by a clock distribution circuit of the data processing device, the differential FS/N frequency clock;
- generating, by a squarer circuit, a single-ended frequency clock from the distributed differential FS/N frequency clock;
- and
- converting, by a converter, the single-ended frequency clock to a differential frequency clock for use at a data processing channel of the data processing device.
A device comprising:
- a clock generation circuit configured to generate a 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2;
- a squarer circuit configured to generate a single-ended frequency clock from the differential FS/N frequency clock;
- a clock distribution circuit configured to distribute the single-ended frequency clock;
- and
- a converter configured to convert the distributed single-ended frequency clock to a differential frequency clock for use at a data processing channel of the data processing device.
Dependencies are inferred from the claim text.