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US 2022/0166432 A1Published application
Complementary depletion mode logic
AssigneeHyperion Semiconductors Oy
InventorArtto AUROLA
Life of this patent
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Abstract
Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.
Claims20
A semiconductor logic element comprising
- a depletion mode field effect transistor of the first conductivity type hereinafter referred to as a first FET comprising a first source, a first drain, a first gate, and a first channel, and
- a depletion mode field effect transistor of the second conductivity type hereinafter referred to as a second FET comprising a second source, a second drain, a second gate, and a second channel;
- wherein the semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the first drain and the second gate,
- wherein the first gate is hereinafter referred to as an input of the semiconductor logic element, wherein the input is configured to be coupled either to a first input logic potential or to a second input logic potential,
- wherein the second drain is referred to as an output of the semiconductor logic element,
- wherein the second source is a source of the semiconductor logic element,
- wherein the semiconductor logic element is configured so that when the first source is arranged at a first source potential and when the second source is at a first output logic potential and when the input is at the first input logic potential, then the first channel is arranged to be in a conductive stage and adjusting the internal node to the first source potential and thereby causing the second channel to be in a nonconductive state thus enabling the output of the semiconductor logic element to be either at the first output logic potential or at a second output logic potential, and
- wherein the semiconductor logic element is further configured so that when the first source is arranged at the first source potential and when the second source is at the first output logic potential and when the input is at the second input logic potential, then the first channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the second channel to be in a conductive state thereby adjusting the output to the first output logic potential.
5 more elements
A first semiconductor logic element comprising
- a field effect transistor of the p type hereinafter referred to as the third FET comprising a third source, a third drain, a third gate, and a third channel, and
- a field effect transistor of the n type hereinafter referred to as the fourth FET comprising a fourth source, a fourth drain, a fourth gate, and a fourth channel;
- wherein the first semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the third drain and the fourth gate, wherein the third gate is hereinafter referred to as an input of the first semiconductor logic element, wherein the input is configured to be coupled either to a third input logic potential or to a fourth input logic potential, wherein the fourth drain is referred to as an output of the first semiconductor logic element,
- wherein the fourth source is a source of the first semiconductor logic element,
- wherein the first semiconductor logic element is configured so that when the third source is arranged at a third source potential and when the fourth source is at a third output logic potential and when the input is at the third input logic potential, then the third channel is arranged to be in a conductive stage adjusting the internal node to the third source potential and thereby causing the fourth channel to be in a nonconductive state thus enabling the output of the first semiconductor logic element to be either at the third output logic potential or at a fourth output logic potential, and
- wherein the first semiconductor logic element is further configured so that when the third source is arranged at the third source potential and when the fourth source is at the third output logic potential and when the input is at the fourth input logic potential, then the third channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the fourth channel to be in a conductive state thereby adjusting the output to the third output logic potential.
3 more elements
A second semiconductor logic element comprising
- a field effect transistor of the n type hereinafter referred to as the fifth FET comprising a fifth source, a fifth drain, a fifth gate, and a fifth channel, and
- a field effect transistor of the p type hereinafter referred to as the sixth FET comprising a sixth source, a sixth drain, a sixth gate, and a sixth channel;
- wherein the second semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the fifth drain and the sixth gate, wherein the fifth gate is hereinafter referred to as an input of the second semiconductor logic element, wherein the input is configured to be coupled either to a fifth input logic potential or to a sixth input logic potential,
- wherein the sixth drain is referred to as an output of the second semiconductor logic element,
- wherein the sixth source is a source of the second semiconductor logic element,
- wherein the second semiconductor logic element is configured so that when the fifth source is arranged at a fifth source potential and when the sixth source is at a fifth output logic potential and when the input is at the fifth input logic potential, then the fifth channel is arranged to be in a conductive stage adjusting the internal node to the fifth source potential and thereby causing the sixth channel to be in a nonconductive state thus enabling the output of the second semiconductor logic element to be either at the fifth output logic potential or at a sixth output logic potential, and
- wherein the second semiconductor logic element is further configured so that when the fifth source is arranged at the fifth source potential and when the sixth source is at the fifth output logic potential and when the input is at the sixth input logic potential, then the fifth channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the sixth channel to be in a conductive state thereby adjusting the output to the fifth output logic potential.
4 more elements
Dependencies are inferred from the claim text.