Method for power brake staggering and in-rush smoothing for multiple endpoints
AssigneeDell Products L.P.
InventorsJeffrey L. Kennedy, Timothy M. Lambert, Yuchen Xu
Life of this patent
Estimating the term…
Abstract
Systems and methods for staggering the release of multiple endpoints from a power brake event. A MCU on each riser implements a riser offset delay based on its position in an order in which power is to be released. For a riser with multiple slots, a delay circuit may be connected to one or more slots to provide a unique offset time to delay the release of power supply the slot. In some systems, a baseboard management controller (BMC) identifies endpoints subject to a power brake event during a POST process. Risers and slots that are not subject to a power brake event are identified and not included in the determination of delays or offset times.
Claims20
A system for controlling power to multiple endpoints, the system comprising:
- a baseboard management controller (BMC) comprising a set of BMC instructions to:
- identify a set of risers subject to a power brake event;
- determine an order for releasing power to each riser of the set of risers;
- and
- communicate the order to a complex programmable logic device (CPLD), the CPLD configurable to communicate a first signal to assert a power brake event and communicate a second signal to de-assert the power brake event;
- and
- a microcontroller unit (MCU) on a riser of the set of risers, the MCU comprising:
- a MCU processor;
- and
- a set of MCU instructions executable by the MCU processor to:
- communicate with the BMC to determine a source connector instance identifier for the riser;
- determine a riser offset time for the riser based on the source connector instance identifier for the riser;
- and
- in response to receiving the first signal from the CPLD to assert the power brake event, throttle power to a set of slots on the riser;
- in response to receiving the second signal from the CPLD to de-assert the power brake event, release power to the set of slots on the riser based on the riser offset time.
An information handling system, comprising:
- a baseboard management controller (BMC) comprising a set of BMC instructions to:
- identify a set of risers subject to a power brake event;
- determine an order for releasing power to each riser of the set of risers;
- and
- communicate the order to a complex programmable logic device (CPLD) having a set of CPLD instructions to communicate a first signal to the set of risers to assert a power brake event and communicate a second signal to the set of risers to de-assert the power brake event;
- and
- a microcontroller unit (MCU) on a riser of the set of risers, wherein the MCU is configured to;
- communicate with the BMC to determine the order that power will be released to the riser;
- determine a riser offset time for the riser based on the order that power will be released to the riser;
- and
- in response to receiving the first signal from the CPLD to assert the power brake event, throttle power to a set of slots on the riser;
- and
- in response to receiving the second signal from the CPLD to de-assert the power brake event, release power to the set of slots on the riser based on the riser offset time.
A method for releasing multiple endpoints from a power brake event, the method comprising:
- determining, by a baseboard management controller (BMC), a set of risers receiving power in an information handling system;
- determining a source connector instance identifier for each riser of the set of risers;
- determining a set of slots on each riser;
- calculating an offset time for each slot based on the source connector instance of the riser and the number of slots on the riser;
- and
- communicating, to a microcontroller unit (MCU) on a riser, the offset time for each slot based on the source connector instance identifier and the number of slots on the riser, wherein
- in response to receiving a first signal from a complex programmable logic device (CPLD) to assert the power brake event, the MCU throttling power to the set of slots;
- and
- in response to receiving a second signal from the CPLD to de-assert the power brake event, the MCU releasing power to each slot of the set of slots based on the offset time for the slot.
Dependencies are inferred from the claim text.