Synchronization signal generating circuit, chip and synchronization method and device, based on multi-core architecture

A synchronization signal generating circuit for generating a synchronization signal for M node groups, each of the node groups comprising at least one node, and M being an integer greater than or equal to 1, wherein

• the synchronization signal generating circuit comprises:
• a synchronization signal generating sub-circuit and M group ready signal generating sub-circuits;
• the M group ready signal generating sub-circuits are in one-to-one correspondence with the M node groups;
• a first group ready signal generating sub-circuit of the M group ready signal generating sub-circuits is connected to K nodes in a first node group to be synchronized, wherein the first group ready signal generating sub-circuit is configured to generate a first to-be-started signal for the first node group to be synchronized, and K is an integer greater than or equal to 1;
• output terminals of the M group ready signal generating sub-circuits are connected to the synchronization signal generating sub-circuit;
• and
• the synchronization signal generating sub-circuit generates a first synchronization signal based on the first to-be-started signal, wherein the first synchronization signal is configured to instruct the K nodes in the first node group to start synchronization.