Programmable delay line with glitch suppression
AssigneeAnalog Devices, Inc.
InventorJohn KENNEY
Life of this patent
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Abstract
There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.
Claims8
A delay circuit, comprising:
- a capacitor and transistor subassembly coupled to an input of the delay circuit;
- a first buffer coupled between the capacitor and transistor subassembly and an output of the delay circuit;
- a second buffer coupled to the output of the delay circuit;
- and
- a latch coupled to the capacitor and transistor subassembly, wherein the latch is to receive an output of the second buffer as a trigger for the latch, wherein the latch is to control conduction of the capacitor and transistor subassembly, and wherein the capacitor and transistor subassembly is to apply a delay to a signal applied to the input of the delay circuit when the capacitor and transistor subassembly is conducting.
8-20. (canceled)
Dependencies are inferred from the claim text.