Word line drive circuit and dynamic random access memory
AssigneeChangxin Memory Technologies, Inc.
InventorCheng-Jer YANG
Life of this patent
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Abstract
The application provides a Word Line (WL) drive circuit and a Dynamic Random Access Memory (DRAM). The WL drive circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate of the first transistor is connected to a WL switch-off voltage, a drain is connected to the WL; a gate of the second transistor is connected to a first drive voltage of the WL, a drain is connected to the WL; and a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor.
Claims18
A Word Line (WL) drive circuit, comprising a first transistor, a second transistor, a third transistor and a fourth transistor, wherein
- a gate of the first transistor is connected to a WL switch-off voltage, and a drain of the first transistor is connected to a WL;
- a gate of the second transistor is connected to a first drive voltage of the WL, and a drain of the second transistor is connected to the WL;
- a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor;
- and
- a drain of the fourth transistor is connected to the WL, a source of the fourth transistor is connected to a second drive voltage of the WL, and a gate of the fourth transistor is connected to the WL switch-off voltage.
A Dynamic Random Access Memory (DRAM), comprising a Word Line (WL) and a WL drive circuit, the WL drive circuit being connected to the WL and comprising a first transistor, a second transistor, a third transistor and a fourth transistor, wherein
- a gate of the first transistor is connected to a WL switch-off voltage, and a drain of the first transistor is connected to the WL;
- a gate of the second transistor is connected to a first drive voltage of the WL, and a drain of the second transistor is connected to the WL;
- a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor;
- and
- a drain of the fourth transistor is connected to the WL, a source of the fourth transistor is connected to a second drive voltage of the WL, and a gate of the fourth transistor is connected to the WL switch-off voltage.
Dependencies are inferred from the claim text.