DRAM with inter-section, page-data-copy scheme for low power and wide data access

An apparatus for page-data accessing in a memory chip, the apparatus comprising:

• a plurality of memory banks, each bank comprising a plurality of sections, each memory section comprising a plurality of memory cells coupled by a word line, each memory cell of a section having a bit line electrically coupled or selectively electrically coupled to a first bit line of a memory cell in an adjacent section via a first latch located at an end of the bit line and electrically coupled or selectively electrically coupled to a second bit line of another memory cell in another adjacent section via a second latch located at another end of the bit line;
• and continuously the bit line of the adjacent memory sections coupled to a bit line in the next section through a next propagating latch module until a bit line at an end of the memory bank is reached;
• and a propagating control unit, coupled to the latch module of each memory section, arranged to perform the signal propagating through bit lines.